Shanghai Key Laboratory of Multidimensional Information Processing and the Department of Electrical Engineering, East China Normal University, Shanghai 200241, China
† Corresponding author. E-mail:
xjli@ee.ecnu.edu.cn
1. IntroductionWith complementary metal-oxide semiconductor (CMOS) technology continuously scaling down, the three-dimensional (3-D) fin field-effect transistor (FinFET) device has become the mainstream due to its better electrostatic control and reduced junction capacitance.[1–3] However, not only does the 3-D structure lead to a new electric field distribution in the channel and affect the I–V characteristics,[4] but also it complicates the parasitic capacitance of the FinFET device. The gate-source/drain parasitic capacitance is gradually dominating the total capacitance of the device,[5–8] and a FinFET structure with dual-k spacer will see the more deteriorated influences.[9]
In order to account for the change of the dual-k spacer, it is necessary to develop an accurately analytical capacitance model. Several models have been reported. Liu et al.[10] proposed a compact model of fringing capacitance for planar MOSFETs. Lee et al.[11] provided a parasitic capacitance model for multi-fin tri-gate FinFET by conformal mapping and non-dimensionalization techniques with several fitting parameters. Chauhan et al.[12] came up with a common parasitic capacitance model, solving the capacitance by an electromagnetic field approximate calculation. Unfortunately, all of them failed to cover the dual-k materials of inter-layer dielectric (ILD) and spacer. The improved approach given by Lacord et al.[13,14] adopted the equivalent permittivity to cover the multilayers materials by approximating the electric fields. However, the singularity in the formula limits its application when the two plates of the capacitor are axial symmetrical. Therefore, the analytical parasitic model for multilayer materials needs to be further explored.
In this paper, an accurate analytical model for 3-D FinFET parasitic capacitance is proposed using the conformal coordinate mapping. The model is geometry-dependent and the different dual-k spacer structures are thoroughly analyzed. The modeling strategy of the fringe capacitance is explained in Section 2. The transfer of the Cartesian coordinate to the elliptic coordinate and the modeling of the capacitance for the dual-k spacer are discussed in Section 3. Section 4 validates our proposed model by comparing the calculation with the TCAD simulation. The conclusions are given in Section 5.
2. Fringe capacitance considering dual-k spacerAs shown in Fig. 1, the parasitic fringe capacitance of the dual-k spacer FinFET device can be divided into six parts, including the gate-to-source/drain (S/D) parallel-plate capacitance 
, the gate-to-fin top capacitances 
and 
, the gate-to-fin side capacitances 
and 
, and the gate-to-source/drain (S/D) side 
. The total parasitic fringe capacitance of the FinFET device from the gate-to-source/drain can be generalized to
 | |
The different materials of spacer and ILD complicate the variety of the gate around parasitic capacitance. In order to achieve accurate modeling of 
, the two-layer structures must be thoroughly analyzed. 
, 
, 
, and 
are generalized to the vertical structure whose material boundaries adhere to the metal plates. Because 
is only a small proportion of 
, it can be approximated as the generalized vertical structure by replacing 
with 
, as shown in Fig. 2. Compared with the total parasitic capacitance, the error from this approximation can be ignored. For the multi-fin structure, the fringe capacitance of gate-to-source/drain is rewritten as
where
N is the number of fins, and
is the parallel capacitance between two fins. Due to the multi-fins sharing the same raised S/D, the parallel-plate capacitors of
and
can be written as
where
is the fin pitch,
is the channel length,
is the distance between two top sides from fin to gate,
is the oxide thickness,
is the S/D width which is smaller than
for
N = 1,
is the fin height,
is the fin width,
is the distance from the spacer to S/D, and
is the spacer thickness. In general, the parallel capacitor
between two fins is larger than
of the single-fin FinFET device because a larger area is introduced, as shown in Fig.
1(b).
3. Capacitance modelingThe generalized capacitance mentioned above consists of two parts, as shown in Fig. 3,
and
are formed as the fusiform (purple colored) and elliptic electric field lines, respectively. Both of the confocal and non-confocal cases will be discussed. Here, the confocal condition is defined as
where
f is the focus length, and (
) and (
) represent the lengths of two plates.
3.1. Confocal capacitance structureThe Cartesian coordinate system can be built-up referring to the two vertical metal plates, as shown in Fig. 4.
3.1.1. Capacitance C0The bent electric field lines shown in Fig. 4(a) can be transferred into the straight counterparts shown in Fig. 4(b) using a coordinate transformation. Then, the fringe capacitance can be formulated using the parallel-plate form. The distances from 
and 
to the coordinate origin decide the location of the ellipse focus, on either the Y-axis or the X-axis. The bent electrical lines (
, 
, 
, 
) in the first quadrant can be transformed. The following mapping can be applied:[15]
As shown in Fig. 4(a), the point 
, 
) indicates the cross point of the field line and the material boundary. There is
Note that the equivalent cross points of the electrical lines are approximated to be on a straight line. With the help of differential quadrature element method (DQEM), the capacitance element can be considered as two capacitors connected in series as
where
ε0 is the vacuum permittivity,
and
are the relative dielectric constants of the spacer and ILD, respectively, and
W is the width of the capacitor in
z-direction. Integrating the capacitance of
C0 from
to
leads to (in units of F)
If the ILD and spacer have the same permittivity, then equation (12) can be simplified as
Again, consider that the ellipse focus is on the Y-axis, giving 
. Due to the symmetry of x and y in the above formulas, after the exchange of x and y in Eqs. (7) and (8), the transformed coordinates are shown in Fig. 4(c), and the updated 
is rewritten as
Therefore, C0 can be obtained by Eq. (12). Depending on 
or 
, either equation (9) or (14) will be chosen to calculate 
.
3.1.2. Capacitance 
For the inner corner part, giving 
and 
, the electric field lines are neither elliptical nor straight, shown as the part close to the corner in Fig. 5. For simplicity, the equivalent capacitor is considered as a parallel structure whose dielectric thickness is approximated as the distance between these two plates, denoted as L. Therefore, D/2 is the maximum distance between the marked line (
) and ellipse (
, 
) in the first quadrant, as shown in Fig. 5. The maximum distance between the outermost electric field lines is defined as D. Given a fixed L, the electronic field is affected by D and written as
where
θ is the phase angle of the ellipse coordinate. Therefore, the inner capacitance can be calculated as (in units of F)
where
is a fitting factor and
W is the width of the capacitor in
z-direction. Combining Eqs. (
12) and (
17), we can calculate the parasitic fringe capacitance of the dual-
k spacer for a FinFET device.
3.2. Non-confocal condition modelBesides the confocal case, the non-confocal case is more general where (
, 
, 
, 
) does not satisfy the confocal requirement of Eq. (6). The model under confocal should be extended to be suitable for the non-confocal situation. As shown in Fig. 6, 
and 
are replaced by the effective counterparts 
and 
when calculating the capacitance C0. Here, 
and 
satisfy the confocal condition, and they are expressed as
The non-confocal can be thought of as a confocal part and an extra part occupied by the dotted lines. According to Fig. 6, in order to make the confocal part largest, the effective lengths should be calculated by
For instance, giving 
, 
, 
, and 
, the effective lengths are written as 
, 
. In view of the non-confocal impact, the factor 
is introduced to reflect the extra part, written as
where
is a fitting factor. Equation (
3) can be written as
Combining Eqs. (10), (17), and (21) into Eq. (22), we can obtain the general expression of the fringe capacitance component
Table 1 summarizes all corresponding parameters for the proposed model of the generalized vertical structures. Therefore, by substituting Eq. (23) into Eq. (2) and using Table 1, we can calculate the total parasitic capacitance of the FinFET device.
Table 1.
Table 1.
 | Table 1.
Parameters for FinFET parasitic capacitors.
. |
4. Model validation and analysisIn order to validate our proposed model, the comparisons between the calculation and the TCAD numerical simulation have been carried out.[16] The validations consist of the single vertical dual-k capacitor and the total FinFET parasitic capacitance. Several materials are considered, including the default nitride (
), high-k HfO2 (
), SiO2 (
), and low-k SiO2 (
) ILD.
In order to extract the total parasitic capacitance 
, TCAD AC simulations of 3-D FinFET have been carried out. During the simulations, the fins are replaced by a metal strip to omit other capacitors of the device. The snapshot of the simulated structures and schematic are shown in Fig. 8. 
can be obtained by subtracting 
from 
. The 14 nm technology node is chosen for the validation of our proposed model. Table 2 shows the default parameters of 14 nm FinFET device.[17,18]
Table 2.
Table 2.
| Table 2.
Default parameters of 14 nm FinFET.
. |
The results in Fig. 9 validate the model accuracy in different material combinations condition, including both the same and different materials. The relative errors between the numerical simulation with TCAD and our model are shown. In each subfigure, 500 simulation cycles have been carried out with randomized 
, 
, 
–
, 
–
, which independently and evenly distributed between 5 nm and 50 nm. This means that all the confocal and non-confocal conditions are covered. The most left-top subfigure shows the result of the same material (
) adopted in the spacer and ILD. The related fitting parameters 
and 
are 0.7 and 2.07, respectively, and the standard deviation (
) of the relative error is 3.51%. The right-top subfigure is based on different materials (
and 
), where the fitted 
and 
are 0.47 and 2.3, and the σ of the relative error is 5.39%. Comparing the lefts with the rights, we can find that the combinations of different materials have larger σ. All the relative errors fall within ±15%, and the minimum and maximum σ of these different cases are 3.20 and 6.83, respectively. The errors become larger as the permittivity difference between the two materials increases. The approximation of materials’ boundary in the elliptic coordinate and concise non-confocal treatment may be the causes.
Figure 10(a) shows that the parasitic capacitance is almost constant under varied fin width. The reason can be found in Fig. 10(b), which implies that the loss of 
is compensated by the increasing 
with the increasing fin width. The increase of the spacer thickness from 3 nm to 10 nm can bring a relatively large change in 
, as shown in Fig. 10(c). The varied fin height and gate height maintain the similar slope for different material combinations, as shown in Figs. 10(d) and 10(e). Figures 10(f) and 10(g) indicate the influences of the fin pitch and fin number on the parasitic capacitance. Among the above parameters of FinFET, except the fin number, the parasitic capacitance is more sensitive to the spacer thickness than the others, especially for high-k spacer materials. It can be concluded that good agreement between our model and TCAD numerical simulation is obtained, even if the fin number, spacer thickness, gate height, fin pitch, or fin number is varied.
5. ConclusionAn accurate analytical model of FinFET parasitic capacitance has been proposed. Not only does it cover the dual-k materials of ILD and spacer, but also it breaks the limitation in the previous capacitance model of dual-k materials. Moreover, only two fitting parameters are introduced. TCAD numerical simulations demonstrate the validation of our proposed model for FinFET parasitic capacitance.
